This invention relates to a video data arranging method for arranging macroblocks in a plurality of parallel accessible banks of a frame memory and to a video processor for processing macroblock by macroblock the video data by using the frame memory, wherein the frame memory is particularly an SDRAM (synchronous dynamic random access memory) capable of high-speed data transfer.
In the manner which will later be described in greater detail, a conventional video processor of this type comprises a video processing unit for compression encoding, as by an MPEG (Moving Picture Experts Group) scheme, the video data into an encoded bit stream based on macroblocks read from the frame memory. The MPEG scheme is featured by an appreciable decrease in an amount of information by the so-called motion compensation of using correlation among a succession of the video data, each of which may be a frame or a field. Although each macroblock should be a square area consisting in each video datum of sixteen by sixteen picture elements or pels in the MPEG scheme, no restriction is imposed therein on the manner of compression encoding. It is therefore possible to make the video processing unit have an optional structure even when the MPEG scheme is used.
Such a video processor is described in a paper presented by A. Ohtani and ten others to the IEEE 1995 Custom Integrated Circuit Conference, pages 405 to 408 or 17.4.1 to 17.4.4, under the title of "A Motion Estimation Processor for MPEG2 Video Real Time Encoding at Wide Search Range". In this paper, a search range input interface is described to a certain extent for use in generating an address signal of the frame memory consisting presumably of banks of the SDRAM. Such banks are, however, referred to merely as external Synchronous-DRAM's (SDRAM's) with no mention to their details.
In general, each bank of the frame memory comprises a plurality of memory sequences which may be memory rows consecutively arranged in memory columns and consist of memory cells serially given memory addresses, respectively, in each of the banks. As for the video data, each video datum comprises the macroblocks in macroblock rows and macroblock columns. Each macroblock comprises a plurality of picture element rows and a plurality of picture element columns, such as a matrix of sixteen picture element rows and sixteen picture element columns. Each picture element row is alternatively called a subblock which is used in the video processor as a signal burst having a burst length of sixteen picture elements and may consist of a plurality of words, such as four words. The video data are supplied to the video processor according to a raster scan and may be of the NTSC technique comprising luminance data Y, blue chrominance data Cb, and red chrominance data Cr. Amounts of data of such luminance and chrominance data are dependent on the manner of encoding and may be 4:4:4, 4:2:2, 4:2:0, or the like. Although specified in the MPEG scheme, each macroblock may have an area dependent on an efficiency of the motion compensation and an amount of overhead information of motion vectors which must somehow be searched in the macroblocks in order to implement the motion compensation. It will be surmised mainly throughout the following that the banks are two in number and are a bank A and another bank B.
In the conventional video processor described above, the picture elements of consecutive subblocks in each macroblock are assigned alternatingly to the banks A and B. More particularly, let a certain one of the macroblock consist of subblocks N, N+1, . . . , and N+15, where N represents an integer identifying the macroblock under consideration in one of the video data. In the video processor being described, a read or write command is issued cyclically to the banks, such as the banks A and B, to transfer the words of each subblock in connection as the signal burst.
It is possible to presume without loss of generality that the read or write command first indicates the memory address of one of the memory cells that is assigned in the bank A to a leading or leftmost picture element of the subblock N. Next, the read or write command indicates the memory address of one of the memory cells that is in the bank B for the leading picture element of the subblock N+1. For one of the macroblock that is under consideration, the read or write command eventually indicates in the bank B the memory addresses of a different one of the memory cells that is for the leading picture element of the subblock N+15. In this manner, the video data are wholly transferred as sixteen signal bursts in connection with the macroblock in question.
In connection with the two or more banks in general, it should be noted on accessing a specified one of the memory sequences leaving a preceding one of the memory sequences that the read or write command must be accompanied by an active command for preliminarily activating memory addresses of the specified one of the memory sequences. On accessing a succeeding one of the memory sequences leaving the specified one of the memory sequences, the read or write command must be accompanied by a precharge operation for subsequently precharging the specified one of the memory sequences. Alternatively, it is known to substitute a read or write auto-precharge command for a combination of the read or write command and the precharge command in automatically precharging the specified one of the memory sequences after read or write of the specified memory sequence.
It may be mentioned here that the video processor is kept in operation by a system clock of a clock period. Several clock periods are necessary in general for activation or precharge of the specified one of the memory sequences. On the other hand, it has been mandatory in the conventional video processor to change or switch a sequence or row address signal every time when the data transfer is completed in connection with each subblock of the macroblock. It has therefore been impossible with the conventional video processor to achieve a raised efficiency of the data transfer and to thereby provide a video data arranging method and a video processor which are of the type described before and are operable at a high speed.